1. Field of the Invention
This invention generally relates to a method for fabricating complementary semiconductor integrated circuits devices and, in particular, this invention relates to the method for fabricating complementary semiconductor integrated circuits devices which are immune to latch-up.
2. Description of the Prior Art
A typical prior art complementary semiconductor integrated circuit (or IC) device is a complementary metal oxide silicon (or CMOS) inverter, schematic plan view of which is shown in FIG. 1A. FIG. 1B is a schematic cross-sectional view of the same prior art CMOS inverter taken along line IB--IB.
As shown, the CMOS inverter comprises P-channel MOS transistor T.sub.P formed on N-type semiconductor substrate 1, and N-channel MOS transistor T.sub.N formed: in the N-type semiconductor substrate. P-channel MOS transistor T.sub.P includes P-type source region 11, P-type drain region 12 and a gate electrode (not shown). When a sufficient negative voltage is applied to the gate electrode, there is formed a P-channel region 15 between source and drain regions 11 and 12. In a similar manner, N-channel MOS transistor T.sub.N includes N-type source region 13, N-type drain region 14 and a gate electrode (not shown). When a sufficient positive voltage is applied to gate electrode 22, there is formed a N-channel region 16 between source and drain regions 13 and 14.
P-type source region 11 of P-channel MOS transistor T.sub.P is provided adjacent to N-type diffusion region 4 in the N-type substrate. Through the N-type diffusion region 4, a supply voltage is applied to the substrate 1. To apply the supply voltage, an aluminum conductor 7 is connected to both P-type source region 11 and N-type diffusion region 4.
Likewise, N-type drain region 14 of N-channel MOS transistor T.sub.N is provided adjacent P-type diffusion region 5 through which a supply voltage is applied to P-well 2. Another aluminum conductor or wire 8 is also connected to N-type drain region 14 and P-type diffusion region 5 in order to connect them to ground.
Aluminum conductor 9 couples drain region 12 of P-channel transistor T.sub.P and source region 13 of N-channel transistor T.sub.N, and forms an output conductor, while aluminum conductor 6 couples the gate electrodes of P- and N-channel transistors T.sub.P, T.sub.N together and constitutes an input conductor.
FIG. 2 shows an equivalent circuit of the CMOS inverter illustrated in FIG. 1A and 1B. The inverter circuit includes P-channel transistor. T.sub.P and N-channel transistor T.sub.N which are series connected with each other between a power supply V.sub.CC and a ground GND.
The operation of the inverter is now described referring to FIG. 2. Input signals to the inverter are simultaneously fed to the gate of both transistors T.sub.N and T.sub.P. When a high level voltage is applied to input conductor 6, transistor T.sub.N is turned on, while transistor T.sub.P is turned off, with the result that the inverter provides a low level voltage as an output signal at output conductor 9. Conversely, application of a low level voltage to the input conductor 6 turns on the transistor T.sub.P and turns off the transistor T.sub.N, and the inverter produces a high level output voltage on output conductor 9.
In producing diffusion regions in manufacturing semiconductor devices, the selective removal of the SiO.sub.2 is required to form openings through which impurities may be diffused. The photoetching method used for this removal is illustrated in FIGS. 3A to 3C. During the photolithographic process the semiconductor substrate is coated with a uniform film of a photosensitive emulsion. A large black-and-white layout of the desired pattern of openings is made and then reduced photographically. This negative, or stencil, of the required dimensions is placed as a mask over the photoresist, as shown in FIG. 3A. By exposure of the emulsion to ultraviolet (UV) light through the mask, the photoresist becomes polymerized under the transparent regions of the stencil. The mask is now removed, and the semiconductor substrate is "developed" by using a chemical (such as trichloroethylene) which dissolves the unexposed unpolymerized) portions of the photoresist film and leaves the surface pattern as shown in FIG. 3B. The emulsion which was not removed in development is now fixed, or cured, so that it becomes resistant to the corrosive etches used next. The chip is immersed in an etching solution of hydrofluoric acid, which removes the oxide from the areas through which dopants are to be diffused. Those portions of the SiO.sub.2 which are protected by the photoresist are unaffected by the acid (FIG. 3C). After diffusion of impurities, the resist mask is removed (stripped) with a chemical solvent (such as hot H.sub.2 SO.sub.4 ) coupled with a mechanical abrasion process. A negative photoresist is used in the process described above. Positive photoresists are also employed in which the exposed portion of the polymer is washed away and thus retains the unexposed material. The remainder of the processing steps are identical and independent of the type of photoresist used.
FIG. 4A through 4E schematically show process steps for manufacturing the conventional CMOS inverter as illustrated in FIG. 1A and 1B by using above described photolithography. In the drawings, various masks which are used in the manufacturing process steps are shown on the right with a reference character b), and cross-sectional portions of the CMOS inverter which corresponds to that shown in FIG. 1B are illustrated on the left with a reference character (a).
First, P-well mask M1 for forming a P-well 2 in the surface of substrate 1 is put in place on the substrate (FIG. 4A). A thin dioxide mask M2 is then placed on the substrate to form a thin oxide layer 20 (FIG. 4B). As a next step, a mask M3 for forming a polysilicon layer 6 on the substrate is overlaid (FIG. 4C). Resulting polysilicon layer 6 forms the input conductor but it is not shown in FIG. 3C since the formed input conductor does not appear in the cross section along line IB--IB of FIG. 1A. P.sup.+ mask M4 is put on the substrate to define P.sup.+ diffusion layer 12 in the surface of the substrate 1 (FIG. 4D). In a final step, N.sup.+ mask M5 is placed on the substrate to define N.sup.+ diffusion layer 13 in the surface of P-well 2 (FIG. 4E).
One problem of the prior art CMOS inverter is that unwanted "parasitic" PNP and NPN transistors are formed in the device. This problem is now described referring to FIG. 5 which shows a cross-section taken along V--V of FIG. 1, and also to FIG. 6 which shows an equivalent circuit of the parasitic transistors of FIG. 5. As shown, P-type source 11, N-type substrate 1 and P-well 2 form a parasitic PNP transistor 23, while N-type substrate 1, P-well 2 and N-type drain 14 form another parasitic NPN transistor 24. Note that a base of NPN transistor 23 and a collector of NPN transistor 24 both comprise the substrate 1. Thus the circuit diagram of FIG. 6 shows an electrical interconnection between a base of PNP transistor 23 and the collector: of NPN transistor 24. In a similar way, a collector of PNP transistor 23 and the base of NPN transistor 24 are shown electrically interconnected with each other because they both comprise P-well 23. In the circuit diagram of FIG. 6, the resistance of the substrate 1 and the resistance of P-well are shown as resistors 25 and 26, respectively.
The operation of parasitic transistors 23 and 24 is described. They are normally biased off. However, lateral current flow in the substrate 1 and P-well 2 can establish potential differences across resistors 25 and 26 which turn on parasitic transistors 23 and 24.
In FIG. 5, node 27 is connected to ground, the aluminum conductor 7 is connected to a positive supply voltage Vcc, typically five volts. Because the resistor 25 is connected between the emitter 11 and the base 1 of PNP transistor 23, the base 1 is always at a lower potential than the emitter 11. Thus, when PNP transistor 3 turns on, a positive voltage is applied to the base 2 of NPN transistor 24. With the emitter 14 of NPN transistor 24 being grounded, transistor 24 turns on, thereby drawing current to ground 27 through resistor 25 from the positive supply voltage Vcc applied to the aluminum conductor 7. This increases the voltage, drop across resistor 25, and the voltage across the emitter-base junction of PNP transistor 23. As a result, transistor 23 is turned on harder. This, in turn, applies a higher voltage to the base of NPN transistor, turning on the same transistor harder. In this manner, current is drawn from positive supply voltage Vcc applied to aluminum conductor 7 through parasitic transistors 23 and 24 to ground 27. This action is called "latch-up". and causes a considerable waste of power in CMOS devices. In some instances, the CMOS inverter is destroyed due to excessive heat generated by the power dissipation through the parasitic transistors.
One approach to minimize latch-up in CMOS devices is described by Estreich et. al. in an article entitled "An Analysis of Latch-up Prevention in CMOS ICs using an Epitaxial Layer Process", IDEM '78 paper 9.7, Dec. 4-6, 1978, Wa. D.C. and by Payne et. al. in an article entitled "Elimination of Latch-up in Bulk CMOS", IDEM '80 paper 10.2, Dec. 8-10, 1980, Wa. D.C. Estreich et. al. and Payne et. al. proposed to utilize epitaxial silicon formed on substrate in an attempt to minimize the sheet resistance of the resistor 25 of FIG. 5. Estreich et. al. further utilize a burried layer to minimize the resistance of resistor 26 of FIG. 5. However, the use of epitaxial silicon and burried layers to minimize sheet resistances requires additional processing steps thus increasing the cost of manufacturing CMOS devices. Moreover, the requirement of additional processing steps introduces product defects and tends to reduce manufacturing yield.
For the benefit of understanding, the construction of a prior art CMOS device having an epitaxial layer grown on its substrate is shown in FIGS. 7A and 7B. This CMOS device is manufactured using the "twin tub process" which is disclosed in detail in a book entitled "Principle of CMOS VLSI Design, A Systems Perspective" (Neil H.F, Weste et. al, 1985, page 89). FIG. 7A is a top plan view of the CMOS device, and FIG. 7B is a cross-sectional view taken along line VIIB--VIIB of FIG. 6A.